Electronic components are generally produced on wafers of semiconductor materials such as silicon, for example.
There are several types of electronic component, corresponding to several types of application, for example power components, on the one hand, and logic or control components, on the other hand. These components may be produced on different wafers, for example bulk wafers, on the one hand, and wafers with a buried insulative layer, on the other hand; the latter are sometimes referred to as silicon on insulator (SOI) wafers when the material of which they are constituted is silicon.
“Bulk” wafers have the particular benefit of enabling the production of so-called vertical components, that is components allowing electrical conduction between the front and rear faces of the wafer. On the other hand, SOI wafers enable the production of components that are totally insulated from each other and from their substrate; this type of wafer is also very widely used to produce MEMS and MOEMS components.
The only example of a material constituting wafers referred to hereinafter is silicon and the only example of a buried layer referred to hereinafter is that of a layer of the relevant oxide (and thus an insulative layer), but it must be understood that other materials, in practice other semiconductor materials, may be used, in particular InP, AsGa, Ge, SixGe1-x, LiNbO3, III-V compounds, II-VI compounds, SiC, diamond, sapphire, and piezoelectric and pyroelectric materials, and that other buried layers are possible.
Moreover, the expression “bulk wafer”, which in the examples to be given hereinafter designates a wafer of a single material, must be understood more generally as being liable to designate a wafer of one or more materials with no buried layer (a fortiori with no insulative buried layer), for example a substrate of silicon under a layer of germanium.
It may be noted that using SOI wafers, the production of which is a proven technology, may be beneficial even if it is unnecessary for the buried layer to be insulative.
It is becoming important to integrate different components into a small volume in order to obtain advanced functions. For many applications, combining components produced on a bulk material with components produced on an SOI material has many advantages, since it enables in particular the production of power components with their logic circuits or with sensors, etc.
One way to combine these different component types is to produce them on the same wafer, which is possible using wafers consisting in part of bulk regions and in part of SOI regions.
Mixed wafers or mixed substrates of this kind have many advantages, including:                they enable the production of both components that are totally insulated from each other and components that function vertically, that is they enable electrical conduction across the volume of certain regions of the wafer, and        they enable different types of function to be produced independently on the same wafer: electrical and/or mechanical and/or optical.        
Various methods of fabricating mixed substrates of this kind are described in the following documents in particular:                U.S. Pat. No. 6,096,433 (NEC Corp), which aims to eliminate the drawbacks of a prior art solution whereby a laminated substrate (that is a substrate comprising a stack of layers) is fabricated from two semiconductor wafers bonded together, one of which has insulative (oxide) regions from place to place on its surface. To prevent the appearance of voids at the interface between the two faces (caused by the different surface state of the Si and SiO2 regions and steps between the two materials), the above document proposes to set the free face of the oxide back relative to the surrounding free face of the silicon, so that there is very good adhesion between the two wafers (in Si and Si regions).        The paper “A new DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)” by K. TERADA, T. ISHIJIMA, T. KUBOTA and M. SAKAO, published in IEEE Transactions on Electron Device, Vol. 37, No. 9, September 1990, pp. 2052-7, which proposes lateral epitaxy of silicon to produce a mixed SOI.        The paper “Intelligent Power IC with partial SOI Structure” by H. YAMAGUCHI, H. HIMI, S. FUJINO and T. HATTORI published in Jpn, J. Appl. Phys. Vol. 34 (1995), pp. 864-868, which proposes etching one of the faces of the wafers to form the future assembly, bonding the two faces, and then filling the cavities formed at the interface in this way with oxide.        
All the above methods use molecular bonding with Si/Si junction regions.
In practice, these Si/Si interfaces should ideally not induce any disturbance in the future components that will utilize these junctions. In particular, it has proved important to be able to minimize impurities in the “bulk” regions, in particular precipitates of oxides, which in particular constitute charge traps that may interfere with good electrical conduction between the two wafers, and the quantity of dislocations caused by misalignment between the two crystals of silicon, which among other things impedes vertical conduction. The above documents do not teach how to guarantee good quality at this interface.
Another type of method is described in the paper “The Fabrication of a Partial SOI Substrate” by D. M. GARNIER, G. ENSELL, J. BONAR, A. BLACKBURN, F. UDREA, H. T. LIM, A. POPESCU, P. L. F. HEMMENT and W. I. MILNE, Proceedings of the 9th International Symposium on Silicon On Isolator Technology and Devices, 1999, Vol. 99, Ch. 54, pp. 73-78, which proposes to create an insulative buried layer having a predetermined pattern, with windows filled with silicon; however, this is not a mixed substrate obtained by molecular bonding, since it is recommended to start with a SIMOX wafer (preferably two wafers bonded together) that is attacked locally through the silicon as far as through the oxide insulative layer; silicon is then grown epitaxially in the windows formed in this way; there is no interface produced by molecular bonding; the above document therefore provides no solution to the problem stated above of producing an interface of good quality.